Large language models (LLMs) have demonstrated immense potential in computer-aided design (CAD), particularly for automated debugging and verification within electronic design automation (EDA) tools. However, Design for Testability (DFT) remains a relatively underexplored area. This paper presents VeriRAG, the first LLM-assisted DFT-EDA framework. VeriRAG leverages a Retrieval-Augmented Generation (RAG) approach to enable LLM to revise code to ensure DFT compliance. VeriRAG integrates (1) an autoencoder-based similarity measurement model for precise retrieval of reference RTL designs for the LLM, and (2) an iterative code revision pipeline that allows the LLM to ensure DFT compliance while maintaining synthesizability. To support VeriRAG, we introduce VeriDFT, a Verilog-based DFT dataset curated for DFT-aware RTL repairs. VeriRAG retrieves structurally similar RTL designs from VeriDFT, each paired with a rigorously validated correction, as references for code repair. With VeriRAG and VeriDFT, we achieve fully automated DFT correction -- resulting in a 7.72-fold improvement in successful repair rate compared to the zero-shot baseline (Fig. 5 in Section V). Ablation studies further confirm the contribution of each component of the VeriRAG framework. We open-source our data, models, and scripts at https://github.com/yuyangdu01/LLM4DFT.

翻译：大型语言模型（LLM）在计算机辅助设计（CAD）领域展现出巨大潜力，尤其是在电子设计自动化（EDA）工具中的自动化调试与验证方面。然而，可测试性设计（DFT）仍是一个相对未被充分探索的领域。本文提出了VeriRAG，首个LLM辅助的DFT-EDA框架。VeriRAG采用检索增强生成（RAG）方法，使LLM能够修改代码以确保符合DFT要求。该框架集成了（1）基于自动编码器的相似性度量模型，用于为LLM精确检索参考RTL设计；（2）迭代式代码修订流程，使LLM在保持可综合性的同时确保DFT合规性。为支持VeriRAG，我们构建了VeriDFT——一个基于Verilog、专为DFT感知的RTL修复而整理的DFT数据集。VeriRAG从VeriDFT中检索结构相似的RTL设计（每个设计均配有经过严格验证的修正方案）作为代码修复的参考。通过VeriRAG与VeriDFT，我们实现了全自动DFT修正——与零样本基线相比，成功修复率提升了7.72倍（见第五节图5）。消融实验进一步验证了VeriRAG框架各组成部分的贡献。我们在https://github.com/yuyangdu01/LLM4DFT 开源了数据、模型及相关脚本。