Recent efforts to improve the performance of neural network (NN) accelerators that meet today's application requirements have given rise to a new trend of logic-based NN inference relying on fixed-function combinational logic (FFCL). This paper presents an innovative optimization methodology for compiling and mapping NNs utilizing FFCL into a logic processor. The presented method maps FFCL blocks to a set of Boolean functions where Boolean operations in each function are mapped to high-performance, low-latency, parallelized processing elements. Graph partitioning and scheduling algorithms are presented to handle FFCL blocks that cannot straightforwardly fit the logic processor. Our experimental evaluations across several datasets and NNs demonstrate the superior performance of our framework in terms of the inference throughput compared to prior art NN accelerators. We achieve 25x higher throughput compared with the XNOR-based accelerator for VGG16 model that can be amplified 5x deploying the graph partitioning and merging algorithms.

翻译：近期为满足现代应用需求而提升神经网络加速器性能的研究催生了一个新趋势：依赖固定功能组合逻辑的逻辑神经网络推理。本文提出了一种创新的优化方法论，用于将采用固定功能组合逻辑的神经网络编译与映射至逻辑处理器。所提出的方法将固定功能组合逻辑模块映射至布尔函数集，其中各函数中的布尔运算被映射至高性能、低延迟、并行化处理单元。针对无法直接适配逻辑处理器的固定功能组合逻辑模块，本文提出了图划分与调度算法。跨多个数据集与神经网络的实验评估表明，与现有神经网络加速器相比，我们的框架在推理吞吐量方面表现出卓越性能。针对VGG16模型，相较于基于XNOR的加速器实现了25倍的吞吐量提升，而通过部署图划分与合并算法，该性能可进一步放大5倍。