Compiling quantum circuits is a major bottleneck in quantum computing, and given the scale required in a few years, is likely to become infeasibly long. Techniques to reduce compilation time for quantum circuits are sorely needed. Furthermore, resources to test acceleration techniques are similarly lacking due to the limited scale of circuits in benchmark suites and mismatches in characteristics of these circuits and those produced by random circuit generators. This paper resolves the latter of these problems by describing a random circuit generator which allows control of circuit density, width and depth parameters. This is used to derive 8000 experimental large-scale circuits and test a novel approach to compiler parallelisation. This separates a circuit into sub-circuits which are compiled in parallel and recombined to produce a compiled circuit. When the parallel approach was tested using Qiskit, a peak speedup of 15.56 was achieved with corresponding overheads of less than 1%.

翻译：编译量子电路是量子计算中的一个主要瓶颈，考虑到未来几年所需的计算规模，其耗时长到可能变得不可行。当前亟需能够减少量子电路编译时间的技术。此外，由于基准测试套件中电路的规模有限，且这些电路与随机电路生成器产生的电路在特性上存在差异，测试加速技术的资源也同样匮乏。本文通过描述一种允许控制电路密度、宽度和深度参数的随机电路生成器，解决了后一个问题。该生成器用于推导出8000个实验性大规模电路，并测试了一种新颖的编译器并行化方法。该方法将电路分割为多个子电路，子电路并行编译后重新组合，最终生成编译后的电路。当使用Qiskit测试这一并行方法时，实现了15.56倍的峰值加速比，相应的开销低于1%。