Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines. However, it is a common belief that these tightly-coupled clusters would not scale beyond a few tens of PEs. In this work, we tackle scaling shared L1 clusters to hundreds of PEs while supporting a flexible and productive programming model and maintaining high efficiency. We present MemPool, a manycore system with 256 RV32IMAXpulpimg "Snitch" cores featuring application-tunable functional units. We designed and implemented an efficient low-latency PE to L1-memory interconnect, an optimized instruction path to ensure each PE's independent execution, and a powerful DMA engine and system interconnect to stream data in and out. MemPool is easy to program, with all the cores sharing a global view of a large, multi-banked, L1 scratchpad memory, accessible within at most five cycles in the absence of conflicts. We provide multiple runtimes to program MemPool at different abstraction levels and illustrate its versatility with a wide set of applications. MemPool runs at 600 MHz (60 gate delays) in typical conditions (TT/0.80 V/25 {\deg}C) in 22 nm FDX technology and achieves a performance of up to 229 GOPS or 180 GOPS/W with less than 2% of execution stalls.

翻译：共享L1存储器集群是构建高效灵活的多处理单元（PE）引擎的常见架构模式（例如在GPGPU中）。然而，人们普遍认为这种紧耦合集群的规模难以突破数十个PE的限度。本研究致力于将共享L1集群扩展至数百个PE，同时支持灵活高效编程模型并维持高能效。我们提出MemPool众核系统，包含256个采用可配置应用功能单元的RV32IMAXpulpimg "Snitch"核心。我们设计实现了高效的PE到L1存储器低延迟互连、优化指令通路以保证每个PE的独立执行，以及用于数据流输入/输出的高性能DMA引擎与系统互连。MemPool编程简便：所有核心共享一个全局大容量多存储体L1便笺式存储器，在无冲突时访问延迟不超过五个时钟周期。我们提供多个运行时环境支持不同抽象层级的MemPool编程，并通过丰富应用案例展示其通用性。在22nm FDX工艺典型条件（TT/0.80V/25°C）下，MemPool运行频率达600MHz（60门延迟），在不到2%的执行停顿率下可实现高达229 GOPS或180 GOPS/W的性能。