Current soft processor architectures for FPGAs do not utilize the potential of the massive parallelism available. FPGAs now support many thousands of embedded floating point operators, and have similar computational densities to GPGPUs. Several soft GPGPU or SIMT processors have been published, but the reported large areas and modest Fmax makes their widespread use unlikely for commercial designs. In this paper we take an alternative approach, building the soft GPU microarchitecture around the FPGA resource mix available. We demonstrate a statically scalable soft GPGPU processor (where both parameters and feature set can be determined at configuration time) that always closes timing at the peak speed of the slowest embedded component in the FPGA (DSP or hard memory), with a completely unconstrained compile into a current Intel Agilex FPGA. We also show dynamic scalability, where a subset of the thread space can be specified on an instruction-by-instruction basis. For one example core type, we show a logic range -- depending on the configuration -- of 4k to 10k ALMs, along with 24 to 32 DSP Blocks, and 50 to 250 M20K memories. All of these instances close timing at 771 MHz, a performance level limited only by the DSP Blocks. We describe our methodology for reliably achieving this clock rate by matching the processor pipeline structure to the physical structure of the FPGA fabric. We also benchmark several algorithms across a range of data sizes, and compare to a commercial soft RISC processor.

翻译：当前用于FPGA的软处理器架构未能充分利用其可用的巨大并行潜力。现代FPGA支持数千个嵌入式浮点运算单元，计算密度已接近GPGPU水平。已有若干软GPGPU或SIMT处理器被报道，但所报告的大面积占用和较低的Fmax使其在商业设计中难以广泛应用。本文采用替代性方法，基于FPGA资源混合特性构建软GPU微架构。我们提出一种静态可扩展的软GPGPU处理器（其参数和功能集可在配置时确定），该处理器始终能在FPGA中最慢嵌入式组件（DSP或硬核存储器）的峰值速度下完成时序收敛，且可无约束地编译至当前Intel Agilex FPGA中。我们还展示了动态可扩展性，即每条指令可指定线程空间的子集。以某一核心类型为例，根据配置不同，其逻辑规模范围为4k至10k个ALM，包含24至32个DSP块，以及50至250个M20K存储器单元。所有这些实例均可在771 MHz频率下达到时序收敛——该性能水平仅受限于DSP块。我们描述了通过将处理器流水线结构与FPGA芯片物理结构相匹配来可靠实现该时钟频率的方法论。最后，我们针对多种数据规模对若干算法进行基准测试，并与商用软RISC处理器进行性能对比。