Emulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidates for such purposes due to their high-speed and reconfigurable architecture. In this paper, we introduce our Makinote, an FPGA-based Cluster platform, hosted at Barcelona Supercomputing Center (BSC-CNS), which is composed of a large number of FPGAs (in total 96 AMD/Xilinx Alveo U55c) to emulate massive size RTL designs (up to 750M ASIC cells). In addition, we introduce our FPGA shell as a powerful tool to facilitate the utilization of such a large FPGA cluster with minimal effort needed by the designers. The proposed FPGA shell provides an easy-to-use interface for the RTL developers to rapidly port such design into several FPGAs by automatically connecting to the necessary ports, e.g., PCIe Gen4, DRAM (DDR4 and HBM), ETH10g/100g. Moreover, specific drivers for exploiting RISC-V based architectures are provided within the set of tools associated with the FPGA shell. We release the tool online for further extensions. We validate the efficiency of our hardware platform (i.e., FPGA cluster) and the software tool (i.e., FPGA Shell) by emulating a RISC-V processor and experimenting HPC Challenge application running on 32 FPGAs. Our results demonstrate that the performance improves by 8 times over the single-FPGA case.

翻译：在流片前对芯片功能进行原型验证至关重要，尤其是随着基于RISC-V的设计日益普及。现场可编程门阵列因其高速可重构架构成为此类应用的理想候选方案。本文介绍由巴塞罗那超算中心（BSC-CNS）部署的Makinote——一种基于FPGA的集群平台。该平台由大量FPGA（共计96片AMD/Xilinx Alveo U55c）组成，可支持大规模RTL设计（最高达7.5亿ASIC逻辑门）的原型验证。此外，我们提出一种FPGA Shell工具，能显著降低设计者使用此类大型FPGA集群的开发门槛。该工具为RTL开发者提供便捷接口，通过自动连接PCIe Gen4、DRAM（DDR4与HBM）、ETH10g/100g等必要端口，可快速将设计移植到多片FPGA。同时，FPGA Shell配套工具集提供专门面向RISC-V架构的驱动支持。我们已将该工具开源以便后续扩展。通过在一台32片FPGA集群上实现RISC-V处理器原型并运行HPC Challenge基准测试，验证了硬件平台（FPGA集群）与软件工具（FPGA Shell）的有效性。实验结果表明，较单FPGA方案性能提升达8倍。