The rise of hardware accelerators with custom instructions necessitates custom compiler backends supporting these accelerators. This study provides detailed analyses of LLVM and its RISC-V backend, supplemented with case studies providing end-to-end overview of the mentioned transformations. We discuss that instruction design should consider both hardware and software design space. The necessary compiler modifications may mean that the instruction is not well designed and need to be reconsidered. We discuss that RISC-V standard extensions provide exemplary instructions that can guide instruction designers. In this study, the process of adding a custom instruction to compiler is split into two parts as Assembler support and pattern matching support. Without pattern matching support, conventional software requires manual entries of inline Assembly for the accelerator which is not scalable. While it is trivial to add Assembler support regardless of the instruction semantics, pattern matching support is on the contrary. Pattern matching support and choosing the right stage for the modification, requires the knowledge of the internal transformations in the compiler. This study delves deep into pattern matching and presents multiple ways to approach the problem of pattern matching support. It is discussed that depending on the pattern's complexity, higher level transformations, e.g. IR level, can be more maintainable compared to Instruction Selection phase.

翻译：硬件加速器伴随自定义指令的兴起，需要支持这些加速器的自定义编译器后端。本研究对LLVM及其RISC-V后端进行了详细分析，并通过案例研究提供了上述转换的端到端概述。我们讨论指出，指令设计应同时考虑硬件和软件设计空间。必要的编译器修改可能意味着指令设计不佳，需要重新审视。我们指出，RISC-V标准扩展提供了可指导指令设计者的示例性指令。在本研究中，将自定义指令添加到编译器的过程分为汇编器支持和模式匹配支持两部分。若缺乏模式匹配支持，传统软件需手动输入加速器的内联汇编，这种做法缺乏可扩展性。虽然无论指令语义如何，添加汇编器支持都相对简单，但模式匹配支持则相反。模式匹配支持及选择恰当的修改阶段，需要掌握编译器内部的转换机制。本研究深入探讨了模式匹配，并提出了解决模式匹配支持问题的多种方法。讨论指出，根据模式复杂度的不同，相较于指令选择阶段，更高层次的转换（例如IR层级）可能更易于维护。