Using accelerators based on analog computing is an efficient way to process the immensely large workloads in Neural Networks (NNs). One example of an analog computing scheme for NNs is Integrate-and-Fire (IF) Spiking Neural Networks (SNNs). However, to achieve high inference accuracy in IF-SNNs, the analog hardware needs to represent current-based multiply-accumulate (MAC) levels as spike times, for which a large membrane capacitor needs to be charged for a certain amount of time. A large capacitor results in high energy use, considerable area cost, and long latency, constituting one of the major bottlenecks in analog IF-SNN implementations. In this work, we propose a HW/SW Codesign method, called CapMin, for capacitor size minimization in analog computing IF-SNNs. CapMin minimizes the capacitor size by reducing the number of spike times needed for accurate operation of the HW, based on the absolute frequency of MAC level occurrences in the SW. To increase the operation of IF-SNNs to current variation, we propose the method CapMin-V, which trades capacitor size for protection based on the reduced capacitor size found in CapMin. In our experiments, CapMin achieves more than a 14$\times$ reduction in capacitor size over the state of the art, while CapMin-V achieves increased variation tolerance in the IF-SNN operation, requiring only a small increase in capacitor size.

翻译：使用基于模拟计算的加速器是处理神经网络中巨大工作负载的高效方式。一种用于神经网络的模拟计算方案是积分-放电（IF）脉冲神经网络（SNN）。然而，为了在IF-SNN中实现高推理精度，模拟硬件需要将基于电流的乘累加（MAC）电平表示为脉冲时间，这需要大膜电容充电特定时长。大电容会导致高能耗、显著的面积开销和长延迟，成为模拟IF-SNN实现的主要瓶颈之一。本文提出一种名为CapMin的软硬件协同设计方法，用于最小化模拟计算IF-SNN中的电容尺寸。CapMin基于软件中MAC电平出现的绝对频率，通过减少硬件精确运行所需的脉冲时间数量来最小化电容尺寸。为增强IF-SNN对电流变化的鲁棒性，我们提出CapMin-V方法，该方法以电容尺寸为代价换取保护能力，其基础是CapMin找到的缩减后电容尺寸。在实验中，CapMin相比现有技术实现了超过14倍的电容尺寸缩减，而CapMin-V在IF-SNN运行中实现了更高的变化容限，仅需小幅增加电容尺寸。