Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before synthesizing circuit elements. Automating this translation could reduce sources of human error from the engineering process. But, it is only recently that artificial intelligence (AI) has demonstrated capabilities for machine-based end-to-end design translations. Commercially-available instruction-tuned Large Language Models (LLMs) such as OpenAI's ChatGPT and Google's Bard claim to be able to produce code in a variety of programming languages; but studies examining them for hardware are still lacking. In this work, we thus explore the challenges faced and opportunities presented when leveraging these recent advances in LLMs for hardware design. Using a suite of 8 representative benchmarks, we examined the capabilities and limitations of the state of the art conversational LLMs when producing Verilog for functional and verification purposes. Given that the LLMs performed best when used interactively, we then performed a longer fully conversational case study where a hardware engineer co-designed a novel 8-bit accumulator-based microprocessor architecture. We sent the benchmarks and processor to tapeout in a Skywater 130nm shuttle, meaning that these 'Chip-Chats' resulted in what we believe to be the world's first wholly-AI-written HDL for tapeout.

翻译：现代硬件设计始于以自然语言提供的规格说明。随后，硬件工程师将这些规格说明转化为适当的硬件描述语言（HDL，如Verilog），再综合为电路元件。实现这一转化过程的自动化可以减少工程流程中人为错误的来源。然而，直到近期，人工智能（AI）才展现出基于机器的端到端设计转换能力。商用指令微调大型语言模型（LLM），例如OpenAI的ChatGPT和Google的Bard，声称能够生成多种编程语言的代码，但针对其在硬件领域能力的研究仍然匮乏。为此，在本工作中，我们探讨了利用近期LLM在硬件设计方面的进步所面临的挑战与机遇。通过一组8个代表性基准测试，我们检验了最先进的对话式LLM在生成功能性及验证性Verilog代码时的能力与局限性。鉴于LLM在交互式使用时表现最佳，我们随后开展了一个完整的长时间对话式案例研究：由硬件工程师协作设计了一款新型8位累加器架构微处理器。我们将基准测试及该处理器提交至Skywater 130nm穿梭项目进行流片，这意味着这些“芯片对话”产生了我们认为世界上首个完全由AI编写的HDL实现流片。