Conventional neural structures tend to communicate through analog quantities such as currents or voltages, however, as CMOS devices shrink and supply voltages decrease, the dynamic range of voltage/current-domain analog circuits becomes narrower, the available margin becomes smaller, and noise immunity decreases. More than that, the use of operational amplifiers (op-amps) and continuous-time or clocked comparators in conventional designs leads to high energy consumption and large chip area, which would be detrimental to building spiking neural networks. In view of this, we propose a neural structure for generating and transmitting time-domain signals, including a neuron module, a synapse module, and two weight modules. The proposed neural structure is driven by a leakage current of MOS transistors and uses an inverter-based comparator to realize a firing function, thus providing higher energy and area efficiency compared to conventional designs. The proposed neural structure is fabricated using TSMC 65 nm CMOS technology. The proposed neuron and synapse occupy the area of 127 {\mu}m^{ 2} and 231 {\mu}m^{ 2}, respectively, while achieving millisecond time constants. Actual chip measurements show that the proposed structure implements the temporal signal communication function with millisecond time constants, which is a critical step toward hardware reservoir computing for human-computer interaction. Simulation results of the spiking-neural network for reservoir computing with the behavioral model of the proposed neural structure demonstrate the learning function.

翻译：传统神经结构倾向于通过电流或电压等模拟量进行通信，然而随着CMOS器件尺寸缩减和供电电压降低，电压/电流域模拟电路的动态范围变窄、可用裕度减小、抗噪声能力下降。此外，传统设计中运算放大器及连续时间/时钟比较器的使用导致高能耗和大芯片面积，这对构建脉冲神经网络极为不利。鉴于此，我们提出一种用于产生和传输时域信号的神经结构，包含神经元模块、突触模块及两个权重模块。该神经结构通过MOS晶体管的漏电流驱动，并采用基于反相器的比较器实现发放函数，从而相比传统设计提供更高的能量与面积效率。该神经结构采用台积电65纳米CMOS工艺制造。所提出的神经元和突触分别占用127 μm²和231 μm²的面积，同时实现毫秒级时间常数。实际芯片测量表明，该结构实现了毫秒级时间常数的时域信号通信功能，这是迈向人机交互硬件储层计算的关键步骤。基于该神经结构行为模型的脉冲神经网络储层计算仿真结果验证了其学习功能。