The proliferation of edge devices necessitates efficient computational architectures for lightweight tasks, particularly deep neural network (DNN) inference. Traditional NPUs, though effective for such operations, face challenges in power, cost, and area when integrated into lightweight edge devices. The RISC-V architecture, known for its modularity and open-source nature, offers a viable alternative. This paper introduces the RISC-V R-extension, a novel approach to enhancing DNN process efficiency on edge devices. The extension features rented-pipeline stages and architectural pipeline registers (APR), which optimize critical operation execution, thereby reducing latency and memory access frequency. Furthermore, this extension includes new custom instructions to support these architectural improvements. Through comprehensive analysis, this study demonstrates the boost of R-extension in edge device processing, setting the stage for more responsive and intelligent edge applications.

翻译：随着边缘设备的普及，针对轻量级任务（尤其是深度神经网络推理）的高效计算架构变得至关重要。传统的神经处理单元虽然在此类运算中表现有效，但在集成到轻量级边缘设备时面临功耗、成本和面积方面的挑战。RISC-V架构以其模块化和开源特性，提供了一个可行的替代方案。本文介绍了RISC-V R扩展，这是一种提升边缘设备上DNN处理效率的新方法。该扩展采用租用流水线阶段和架构流水线寄存器，优化了关键操作的执行，从而降低了延迟和内存访问频率。此外，该扩展还包含新的自定义指令以支持这些架构改进。通过综合分析，本研究展示了R扩展在边缘设备处理中的性能提升，为更具响应性和智能化的边缘应用奠定了基础。