Time-Aware Shaper (TAS) is a time-triggered scheduling mechanism that ensures bounded latency for time-critical Scheduled Traffic (ST) flows. The Linux kernel implementation (a.k.a TAPRIO) has limited capabilities due to varying CPU workloads and thus does not offer tight latency bound for the ST flows. Also, currently only higher cycle times are possible. Other software implementations are limited to simulation studies without physical implementation. In this paper, we present $\mu$TAS, a MicroC-based hardware implementation of TAS onto a programmable SmartNIC. $\mu$TAS takes advantage of the parallel-processing architecture of the SmartNIC to configure the scheduling behaviour of its queues at runtime. To demonstrate the effectiveness of $\mu$TAS, we built a Time-Sensitive Networking (TSN) testbed from scratch. This consists of multiple end-hosts capable of generating ST and Best Effort (BE) flows and TSN switches equipped with SmartNICs running $\mu$TAS. Time synchronization is maintained between the switches and hosts. Our experiments demonstrate that the ST flows experience a bounded latency of the order of tens of microseconds.

翻译：时间感知整形器（TAS）是一种时间触发调度机制，可确保时间关键型调度流量（ST）流的有界延迟。由于CPU工作负载的波动，Linux内核实现（即TAPRIO）能力有限，无法为ST流提供严格的延迟边界，且目前仅支持较高的周期时间。其他软件实现仅限于仿真研究，缺乏物理实现。本文提出μTAS，一种基于MicroC的可编程SmartNIC硬件实现的TAS方案。μTAS利用SmartNIC的并行处理架构，在运行时配置其队列的调度行为。为验证μTAS的有效性，我们从头搭建了时间敏感网络（TSN）测试平台，包含多个可生成ST流和尽力而为（BE）流的端主机，以及配备运行μTAS的SmartNIC的TSN交换机。交换机与主机间保持时间同步。实验表明，ST流的有界延迟可达数十微秒量级。