Posit has been a promising alternative to the IEEE-754 floating point format for deep learning applications due to its better trade-off between dynamic range and accuracy. However, hardware implementation of posit arithmetic requires further exploration, especially for the dot-product operations dominated in deep neural networks (DNNs). It has been implemented by either the combination of multipliers and an adder tree or cascaded fused multiply-add units, leading to poor computational efficiency and excessive hardware overhead. To address this issue, we propose an open-source posit dot-product unit, namely PDPU, that facilitates resource-efficient and high-throughput dot-product hardware implementation. PDPU not only features the fused and mixed-precision architecture that eliminates redundant latency and hardware resources, but also has a fine-grained 6-stage pipeline, improving computational efficiency. A configurable PDPU generator is further developed to meet the diverse needs of various DNNs for computational accuracy. Experimental results evaluated under the 28nm CMOS process show that PDPU reduces area, latency, and power by up to 43%, 64%, and 70%, respectively, compared to the existing implementations. Hence, PDPU has great potential as the computing core of posit-based accelerators for deep learning applications.

翻译：Posit格式因其在动态范围与精度之间的更优权衡，已成为深度学习应用中IEEE-754浮点格式的有力替代方案。然而，Posit算术的硬件实现仍需进一步探索，尤其是针对深度神经网络（DNN）中占主导地位的点积运算。现有实现方式要么采用乘法器与加法树组合，要么采用级联融合乘加单元，导致计算效率低下且硬件开销过大。为解决该问题，我们提出一种开源Posit点积运算单元PDPU，可支持资源高效且高吞吐量的点积硬件实现。PDPU不仅采用消除冗余延迟和硬件资源的融合混合精度架构，还具备细粒度六级流水线设计以提升计算效率。为满足不同DNN对计算精度的多样化需求，进一步开发了可配置的PDPU生成器。在28nm CMOS工艺下的实验评估表明，与现有实现相比，PDPU在面积、延迟和功耗上分别降低最高43%、64%和70%。因此，PDPU作为基于Posit的深度学习加速器计算核心具有巨大潜力。