Probabilistic circuits (PCs) is a unifying representation for probabilistic models that support tractable inference. Numerous applications of PCs like controllable text generation depend on the ability to efficiently multiply two circuits. Existing multiplication algorithms require that the circuits respect the same structure, i.e. variable scopes decomposes according to the same vtree. In this work, we propose and study the task of restructuring structured(-decomposable) PCs, that is, transforming a structured PC such that it conforms to a target vtree. We propose a generic approach for this problem and show that it leads to novel polynomial-time algorithms for multiplying circuits respecting different vtrees, as well as a practical depth-reduction algorithm that preserves structured decomposibility. Our work opens up new avenues for tractable PC inference, suggesting the possibility of training with less restrictive PC structures while enabling efficient inference by changing their structures at inference time.

翻译：概率电路（PCs）是一种支持可处理推理的概率模型的统一表示框架。PCs在可控文本生成等众多应用中的有效性依赖于两个电路高效相乘的能力。现有的乘法算法要求电路遵循相同的结构，即变量作用域必须按照相同的虚拟树进行分解。本研究提出并探讨了结构化（可分解）PCs的重构任务，即将一个结构化PC转换为符合目标虚拟树的形式。我们针对该问题提出了一种通用方法，并证明该方法能够推导出适用于不同虚拟树电路相乘的新型多项式时间算法，以及一种保持结构可分解性的实用深度约简算法。我们的研究为可处理PC推理开辟了新途径，表明可以在训练阶段使用限制较少的PC结构，同时通过在推理阶段改变其结构来实现高效推理。