Measuring a qubit state is a fundamental yet error-prone operation in quantum computing. These errors can arise from various sources, such as crosstalk, spontaneous state transitions, and excitations caused by the readout pulse. Here, we utilize an integrated approach to deploy neural networks onto field-programmable gate arrays (FPGA). We demonstrate that implementing a fully connected neural network accelerator for multi-qubit readout is advantageous, balancing computational complexity with low latency requirements without significant loss in accuracy. The neural network is implemented by quantizing weights, activation functions, and inputs. The hardware accelerator performs frequency-multiplexed readout of five superconducting qubits in less than 50 ns on a radio frequency system on chip (RFSoC) ZCU111 FPGA, marking the advent of RFSoC-based low-latency multi-qubit readout using neural networks. These modules can be implemented and integrated into existing quantum control and readout platforms, making the RFSoC ZCU111 ready for experimental deployment.

翻译：量子比特态测量是量子计算中基础但易出错的操作。这些误差可能源于多种因素，如串扰、自发态跃迁以及读取脉冲引起的激发。本文采用集成化方法将神经网络部署至现场可编程门阵列（FPGA）。我们证明，实现用于多量子比特读取的全连接神经网络加速器具有显著优势，能在计算复杂度与低延迟需求之间取得平衡，且不造成明显的精度损失。该神经网络通过量化权重、激活函数及输入参数实现。硬件加速器在射频片上系统（RFSoC）ZCU111 FPGA上以低于50纳秒的延迟完成了五个超导量子比特的频分复用读取，标志着基于RFSoC的神经网络低延迟多量子比特读取技术的诞生。这些模块可集成至现有量子控制与读取平台，使RFSoC ZCU111具备实验部署条件。