To test and debug hardware modules, it is common to write two programs. A driver maps high-level transactions to cycle-level I/O behavior, and a monitor looks at the low-level I/O trace and recovers transactions. Both programs bridge the same abstraction gap between RTL and functional models. Writing them separately risks inconsistency. ProtoLang is a DSL for specifying hardware protocols. The same ProtoLang program can both drive and monitor transactions. Users specify RTL communication protocols as succinct imperative programs. We present a novel reconstructor algorithm that, given a ProtoLang specification and a waveform, automatically infers a transaction-level trace consistent with the waveform. We demonstrate ProtoLang's utility via case studies focusing on the Wishbone and AXI-Stream interconnects, showing that ProtoLang can model complex protocol features such as burst mode. We highlight how our tools can identify protocol violation bugs in real-world implementations.

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