For years, the open-source RISC-V instruction set has been driving innovation in processor design, spanning from high-end cores to low-cost or low-power cores. After a decade of evolution, RISC architectures are now as mature as the CISC architectures popularized by industry giant Intel. Security and energy efficiency are now joining execution speed among the design constraints. In this article, we assess the benefits and costs associated with integrating a micro-decoding unit inspired by CISC processors into a RISC-V core. This unit, added in a specific pipeline stage, should enable dynamic custom instruction sequences execution whose usage could be, for instance to compress binaries, obfuscate behavior, etc.

翻译：多年来，开源的RISC-V指令集持续推动着处理器设计的创新，其应用范围涵盖从高端内核到低成本或低功耗内核的各个领域。经过十年的发展，RISC架构现已达到与行业巨头英特尔推广的CISC架构同等的成熟度。在当前的设计约束中，安全性和能效已与执行速度同等重要。本文评估了将受CISC处理器启发的微解码单元集成到RISC-V内核中所带来的优势与成本。该单元添加在特定的流水线阶段，旨在支持动态自定义指令序列的执行，其应用场景可包括二进制代码压缩、行为混淆等。