Memristors provide a tempting solution for weighted synapse connections in neuromorphic computing due to their size and non-volatile nature. However, memristors are unreliable in the commonly used voltage-pulse-based programming approaches and require precisely shaped pulses to avoid programming failure. In this paper, we demonstrate a current-limiting-based solution that provides a more predictable analog memory behavior when reading and writing memristive synapses. With our proposed design READ current can be optimized by about 19x compared to the 1T1R design. Moreover, our proposed design saves about 9x energy compared to the 1T1R design. Our 3T1R design also shows promising write operation which is less affected by the process variation in MOSFETs and the inherent stochastic behavior of memristors. Memristors used for testing are hafnium oxide based and were fabricated in a 65nm hybrid CMOS-memristor process. The proposed design also shows linear characteristics between the voltage applied and the resulting resistance for the writing operation. The simulation and measured data show similar patterns with respect to voltage pulse-based programming and current compliance-based programming. We further observed the impact of this behavior on neuromorphic-specific applications such as a spiking neural network

翻译：忆阻器因其尺寸小和非易失性，为神经形态计算中的加权突触连接提供了诱人的解决方案。然而，在常用的基于电压脉冲的编程方法中，忆阻器不可靠，需要精确成形的脉冲以避免编程失败。在本文中，我们展示了一种基于限流的解决方案，该方案在读写忆阻突触时提供了更可预测的模拟存储行为。与1T1R设计相比，我们提出的设计可将读取电流优化约19倍。此外，与1T1R设计相比，我们提出的设计节省了约9倍的能量。我们的3T1R设计还显示出有前景的写入操作，该操作受MOSFET工艺变化和忆阻器固有随机行为的影响较小。用于测试的忆阻器基于氧化铪，并在65nm混合CMOS-忆阻器工艺中制造。所提出的设计在写入操作中显示了施加电压与所得电阻之间的线性特性。仿真和实测数据在基于电压脉冲编程和基于电流合规编程方面表现出相似的模式。我们进一步观察到这种行为对神经形态特定应用（如脉冲神经网络）的影响。