Cache side-channel attacks and speculative execution attacks that leak information through cache states are stealthy and dangerous attacks on hardware that must be mitigated. Unfortunately, defenses proposed for cache side-channel attacks do not mitigate all cache-based speculative execution attacks and vice versa. Since both classes of attacks must be addressed, we propose comprehensive cache architectures to do this. We show a framework to analyze the security of a secure cache. We identify same-domain speculative execution attacks, and show they evade cache side-channel defenses. We present new hardware security mechanisms that address target attacks and reduce performance overhead. We design two Speculative and Timing Attack Resilient (STAR) caches that defeat both cache side-channel attacks and cache-based speculative execution attacks. These comprehensive defenses have low performance overhead of 6.6% and 8.8%.

翻译：缓存侧信道攻击和通过缓存状态泄露信息的推测执行攻击是对硬件的隐蔽而危险的攻击，必须加以缓解。不幸的是，为缓存侧信道攻击提出的防御措施无法缓解所有基于缓存的推测执行攻击，反之亦然。由于这两类攻击都必须解决，我们提出了全面的缓存架构来实现这一目标。我们展示了一个分析安全缓存安全性的框架。我们识别了同域推测执行攻击，并证明它们能规避缓存侧信道防御。我们提出了新的硬件安全机制，以应对目标攻击并降低性能开销。我们设计了两种推测与时序攻击弹性（STAR）缓存，既能抵御缓存侧信道攻击，又能抵御基于缓存的推测执行攻击。这些全面防御导致的性能开销较低，分别为6.6%和8.8%。