Triggerless Data Acquisition Systems (DAQs) require transmitting the data stream from multiple links to the processing node. The short input data words must be concentrated and packed into the longer bit vectors the output interface (e.g., PCI Express) uses. In that process, the unneeded data must be eliminated, and a dense stream of useful DAQ data must be created. Additionally, the time order of the data should be preserved. This paper presents a new solution using the Baseline Network with Reversed Outputs (BNRO) for high-speed data routing. A thorough analysis of the network's operation enabled increased scalability compared to the previously published concentrator based on an 8x8 network. The solution may be scaled by adding additional layers to the BNRO network while minimizing resource consumption. Simulations were done for 4 and 5 layers (16 and 32 inputs). The FPGA implementation and tests in the actual hardware have been successfully performed for 16 inputs. The pipeline registers may be added in each layer independently, shortening the critical path and increasing the maximum acceptable clock frequency.

翻译：无触发数据采集系统（Triggerless DAQs）要求将来自多个链路的数据流传输至处理节点。短输入数据字需经集中与打包处理，转换为输出接口（如PCI Express）所使用的较长位向量。在此过程中，需剔除无效数据，生成密集的有效DAQ数据流，同时保持数据的时间顺序。本文提出一种采用反向输出基线网络（BNRO）的新型高速数据路由方案。通过对网络运行机制的深入分析，相较于此前基于8×8网络的集中器方案，本方案的可扩展性显著提升。通过向BNRO网络逐层扩展可在最小化资源消耗的同时实现系统扩展。针对4层与5层（16路与32路输入）网络进行了仿真验证，并在实际硬件中成功完成了16路输入的FPGA实现与测试。各层可独立添加流水线寄存器，从而缩短关键路径并提高可接受的最大时钟频率。