Two-phase clocking offers significant advantages in timing margin and clock flexibility, yet its adoption remains limited due to the absence of automation in modern design flows. Managing strict non-overlap and 180$^\circ$ phase separation introduces complexity in RTL implementation and timing closure, leaving two-phase clocking rare in practice. This paper presents the first fully automated two-phase clocking flow integrated into OpenROAD Flow Scripts (ORFS). Our methodology automatically transforms flip-flop-based RTL into two-phase latch-based designs using Yosys technology mapping, ABC retiming, dual clock tree synthesis, two-phase correctness validation, and full physical design from RTL-to-GDS. We implement clock-gated and recirculation mux variants, where clock-gated achieves an average 29.2\% power reduction and 50\% latch count reduction over recirculation mux. Both variants are compared against flip-flop baselines, demonstrating timing closure through time borrowing on a design that failed timing with flip-flops.

翻译：双相时钟在时序裕度和时钟灵活性方面具有显著优势，但由于现代设计流程中缺乏自动化工具，其应用仍然有限。管理严格的非交叠和180°相位分离增加了RTL实现和时序收敛的复杂性，使得双相时钟在实践中鲜有应用。本文提出了首个完全自动化的双相时钟流程，并集成到OpenROAD流程脚本（ORFS）中。我们的方法通过Yosys技术映射、ABC重定时、双时钟树综合、双相正确性验证以及从RTL到GDS的完整物理设计，自动将基于触发器的RTL设计转换为双相锁存器设计。我们实现了时钟门控和循环复用器两种变体，其中时钟门控相较于循环复用器平均功耗降低29.2%，锁存器数量减少50%。两种变体均与触发器基线进行对比，通过时序借用展示了时序收敛能力，而采用触发器的设计在时序上无法满足要求。