Modern high-performance computing architectures (Multicore, GPU, Manycore) are based on tightly-coupled clusters of processing elements, physically implemented as rectangular tiles. Their size and aspect ratio strongly impact the achievable operating frequency and energy efficiency, but they should be as flexible as possible to achieve a high utilization for the top-level die floorplan. In this paper, we explore the flexibility range for a high-performance cluster of RISC-V cores with shared L1 memory used to build scalable accelerators, with the goal of establishing a hierarchical implementation methodology where clusters can be modeled as soft tiles to achieve optimal die utilization.

翻译：现代高性能计算结构(多功能、GPU、多核心)以紧密组合的处理元件组合为基础,以矩形砖的形式实际实施,其大小和侧比对可实现的操作频率和能源效率产生强烈影响,但应尽量灵活,以便高利用顶层死亡楼层计划。 在本文件中,我们探讨了高性能的RISC-V核心核心群的灵活性范围,该核心群使用共享的L1内存来建立可缩放加速器,目的是建立分级执行方法,使集群以软砖为模型,实现最佳死亡利用。