Macro placement is a critical phase in chip design, which becomes more intricate when involving general rectilinear macros and layout areas. Furthermore, macro placement that incorporates human-like constraints, such as design hierarchy and peripheral bias, has the potential to significantly reduce the amount of additional manual labor required from designers. This study proposes a methodology that leverages an approach suggested by Google's Circuit Training (G-CT) to provide a learning-based macro placer that not only supports placing rectilinear cases, but also adheres to crucial human-like design principles. Our experimental results demonstrate the effectiveness of our framework in achieving power-performance-area (PPA) metrics and in obtaining placements of high quality, comparable to those produced with human intervention. Additionally, our methodology shows potential as a generalized model to address diverse macro shapes and layout areas.

翻译：宏单元布局是芯片设计中的一个关键阶段，当涉及一般直角宏单元和布局区域时，其复杂性进一步增加。此外，融入类人约束（如设计层次结构和外围偏置）的宏单元布局，能够显著减少设计人员所需的额外人工工作量。本研究提出了一种方法，利用谷歌电路训练（G-CT）所倡导的方案，构建基于学习的宏单元布局器，该布局器不仅支持直角宏单元的放置，还遵循关键的类人设计原则。我们的实验结果表明，该框架在实现功耗-性能-面积（PPA）指标以及获得与人工干预下相媲美的高质量布局方面具有有效性。此外，我们的方法展现了作为通用模型应对多样化宏单元形状和布局区域的潜力。