EDA problems are graph-structured, but not all graph-structured problems call for the same GNN computation. We argue that successful GNN-for-EDA methods are those whose propagation, aggregation, and supervision align with the native algebra of the target task. Concretely: static timing analysis is a max-plus/min-plus recurrence on a topologically ordered DAG, structurally aligned with asynchronous DAG-GNNs; placement is governed by hypergraph wirelength and density penalties and is exploited by differentiable placers rather than by message-passing GNNs alone; routing congestion is a sparse demand-supply field over a layout grid; switching-activity propagation is a probabilistic recurrence on a directed netlist; IR drop is a linear system on the power-delivery network; and analog symmetry extraction is a discrete constraint-prediction problem on schematic graphs. Through these task-by-task alignments we (i) review the GNN architectural toolkit relevant to circuits, (ii) formalize how circuit graphs differ from generic graphs (directed, heterogeneous, multi-scale, with sequential and clock structure), (iii) characterize where current methods succeed and where the algebra-architecture mismatch limits them, and (iv) identify failure modes--stage leakage, proxy-to-signoff gap, calibration, and design-distribution shift--that we believe are likely to dominate the next phase of work. We position the paper as a GNN-for-EDA, task-aligned analysis rather than a comprehensive AI-for-chip-design survey. Continuous SE(3)-equivariant geometric GNNs are usually mismatched to Manhattan digital layout, and LLM-for-RTL, HLS, and RL/diffusion-based topology generation are outside our scope.

翻译：电子设计自动化（EDA）问题本质上是图结构化的，但并非所有图结构化问题都需要相同的GNN计算方式。我们认为，成功的GNN-for-EDA方法的关键在于其传播、聚合与监督机制与目标任务的固有代数结构保持一致。具体而言：静态时序分析是在拓扑有序有向无环图上进行的max-plus/min-plus递推，在结构上与异步DAG-GNN对齐；布局问题受超图线长和密度惩罚项的支配，主要通过可微布局器而非单纯的消息传递GNN来求解；布线拥塞是布局网格上的稀疏供需场；开关活动传播是有向网表上的概率递推问题；IR压降是供电网络上的线性系统；而模拟对称性提取则是原理图图上的离散约束预测问题。通过这些逐任务的对齐分析，我们（i）回顾了与电路相关的GNN架构工具箱；（ii）形式化了电路图与通用图的区别（有向、异质、多尺度、含时序与时钟结构）；（iii）刻画了当前方法的成功之处以及代数-架构不匹配导致的局限性；（iv）识别了我们认为将主导下一阶段工作的失效模式——阶段泄漏、代理指标与流片指标差距、校准以及设计分布偏移。我们将本文定位为面向EDA的GNN任务对齐分析论文，而非全面的AI芯片设计综述。连续SE(3)等变几何GNN通常与曼哈顿数字版图不匹配，而面向寄存器传输级的大型语言模型（LLM-for-RTL）、高层次综合（HLS）以及基于强化学习/扩散的拓扑生成不在本文讨论范围内。