Analog circuit design remains highly dependent on expert knowledge due to the complexity of device-level interactions and topology design. Recent transformer-based approaches for device-level topology generation have shown promise, yet they suffer from low electrical validity without human-in-the-loop (HITL) training and severe memorization caused by sequence-based circuit representations. In this work, we propose AnalogToBi, a framework for device-level analog circuit topology generation. AnalogToBi introduces circuit-type conditioning for categorizing heterogeneous multi-type topology datasets, device renaming augmentation to mitigate memorization, a bipartite graph representation for improved structural generalization, and grammar-guided decoding to enforce structural validity during bipartite graph generation. Experimental results demonstrate that AnalogToBi achieves high validity and novelty without HITL training while effectively avoiding memorization of training topologies. Our code is available at https://github.com/Seungmin0825/AnalogToBi.

翻译：模拟电路设计因器件级交互与拓扑结构的复杂性，始终高度依赖专家经验。现有基于Transformer的器件级拓扑生成方法虽展现出潜力，但存在两大缺陷：无人工参与训练时电学有效性低下，以及基于序列的电路表示导致的严重记忆化问题。为此，我们提出AnalogToBi框架——一种面向器件级模拟电路拓扑生成的方法。该框架引入电路类型条件化机制对异构多类型拓扑数据集进行分类，通过器件重命名增强缓解记忆化现象，采用二分图表示提升结构泛化能力，并设计语法引导解码确保二分图生成过程中的结构有效性。实验结果表明，AnalogToBi无需人工参与训练即可实现高有效性与新颖性，同时有效避免对训练拓扑的记忆化。我们的代码已开源至https://github.com/Seungmin0825/AnalogToBi。