A core objective of physical design is to minimize wirelength (WL) when placing chip components on a canvas. Computing the minimal WL of a placement requires finding rectilinear Steiner minimum trees (RSMTs), an NP-hard problem. We propose NeuroSteiner, a neural model that distills GeoSteiner, an optimal RSMT solver, to navigate the cost--accuracy frontier of WL estimation. NeuroSteiner is trained on synthesized nets labeled by GeoSteiner, alleviating the need to train on real chip designs. Moreover, NeuroSteiner's differentiability allows to place by minimizing WL through gradient descent. On ISPD 2005 and 2019, NeuroSteiner can obtain 0.3% WL error while being 60% faster than GeoSteiner, or 0.2% and 30%.

翻译：物理设计的核心目标之一是在画布上布置芯片组件时最小化线长。计算布局的最小线长需要求解直角斯坦纳最小树，这是一个NP难问题。我们提出了NeuroSteiner，一种从最优RSMT求解器GeoSteiner中提炼知识的神经模型，以探索线长估计在成本与精度之间的权衡边界。NeuroSteiner在由GeoSteiner标注的合成线网上进行训练，无需依赖真实芯片设计数据进行训练。此外，NeuroSteiner的可微特性允许通过梯度下降法直接优化线长进行布局。在ISPD 2005和2019基准测试中，NeuroSteiner能以比GeoSteiner快60%的速度实现0.3%的线长误差，或以快30%的速度实现0.2%的误差。