Modern chip design requires multi-objective optimization of timing, power, and area under stringent time-to-market constraints. Although powerful optimization algorithms are integrated into EDA tools, achieving high QoR hinges on effective long-horizon scheduling, which relies heavily on manual expert intervention. To address this issue and automate chip design, we propose an agentic LLM framework that schedules chip optimizations through direct interaction with EDA tools. The agent is grounded in natural language expertise expressed as a search tree through retrieval-augmented generation (RAG). We further improve scheduling quality with Pareto-driven QoR feedback through language reflection. Experimental results show that, compared with black-box search methods such as reinforcement learning, our framework achieves 10% greater timing improvement while consuming less power and area, with more than 4x speedup. The post-optimization QoR is also comparable to that achieved by human experts. Finally, the agent supports customized tasks expressed in natural language, enabling preferential QoR trade-offs. The code and chip design data will be publicly available at https://github.com/YiKangOY/Open-LLM-ECO.

翻译：现代芯片设计需要在严格的时间约束下对时序、功耗和面积进行多目标优化。尽管电子设计自动化工具集成了强大的优化算法，但实现高质量结果的关键在于有效的长程调度，而这在很大程度上依赖于人工专家干预。为解决此问题并实现芯片设计自动化，我们提出了一种基于智能体的大语言模型框架，该框架通过与电子设计自动化工具直接交互来调度芯片优化过程。该智能体通过检索增强生成技术，将自然语言专业知识构建为搜索树进行知识锚定。我们进一步通过语言反思机制，利用帕累托驱动的质量结果反馈来提升调度质量。实验结果表明，与强化学习等黑盒搜索方法相比，我们的框架在降低功耗和面积的同时，实现了10%的时序改进，且加速比超过4倍。优化后的质量结果也与人类专家实现的效果相当。最后，该智能体支持以自然语言表达的定制化任务，能够实现优先级的质量结果权衡。代码与芯片设计数据将在https://github.com/YiKangOY/Open-LLM-ECO公开。