FPGA technology mapping is the process of implementing a hardware design expressed in high-level HDL (hardware design language) code using the low-level, architecture-specific primitives of the target FPGA. As FPGAs become increasingly heterogeneous, achieving high performance requires hardware synthesis tools that better support mapping to complex, highly configurable primitives like digital signal processors (DSPs). Current tools support DSP mapping via handwritten special-case mapping rules, which are laborious to write, error-prone, and often overlook mapping opportunities. We introduce Lakeroad, a principled approach to technology mapping via sketch-guided program synthesis. Lakeroad leverages two techniques -- architecture-independent sketch templates and semantics extraction from HDL -- to provide extensible technology mapping with stronger correctness guarantees and higher coverage of mapping opportunities than state-of-the-art tools. Across representative microbenchmarks, Lakeroad produces 2--3.5$\times$ the number of optimal mappings compared to proprietary state-of-the-art tools and 6--44$\times$ the number of optimal mappings compared to popular open-source tools, while also providing correctness guarantees not given by any other tool.

翻译：FPGA技术映射是将用高级HDL（硬件设计语言）代码表示的硬件设计，通过目标FPGA底层架构特定原语进行实现的过程。随着FPGA异构化程度日益加深，要实现高性能就需要硬件综合工具更好地支持对数字信号处理器（DSP）等复杂、高度可配置原语的映射。现有工具通过手工编写特殊映射规则来支持DSP映射，但这种方法既费时费力又容易出错，且常常遗漏映射机会。我们提出Lakeroad，一种基于草图导引程序综合的技术映射原则性方法。Lakeroad利用两项技术——架构无关的草图模板和从HDL中提取语义——提供了可扩展的技术映射方法，在正确性保证和映射机会覆盖率方面均优于现有最优工具。在代表性微基准测试中，与专有最优工具相比，Lakeroad产生的最优映射数量多2-3.5倍；与主流开源工具相比，则多6-44倍，同时还提供了其他工具所不具备的正确性保证。