Placement is a critical and challenging step of modern chip design, with routability being an essential indicator of placement quality. Current routability-oriented placers typically apply an iterative two-stage approach, wherein the first stage generates a placement solution, and the second stage provides non-differentiable routing results to heuristically improve the solution quality. This method hinders jointly optimizing the routability aspect during placement. To address this problem, this work introduces RoutePlacer, an end-to-end routability-aware placement method. It trains RouteGNN, a customized graph neural network, to efficiently and accurately predict routability by capturing and fusing geometric and topological representations of placements. Well-trained RouteGNN then serves as a differentiable approximation of routability, enabling end-to-end gradient-based routability optimization. In addition, RouteGNN can improve two-stage placers as a plug-and-play alternative to external routers. Our experiments on DREAMPlace, an open-source AI4EDA platform, show that RoutePlacer can reduce Total Overflow by up to 16% while maintaining routed wirelength, compared to the state-of-the-art; integrating RouteGNN within two-stage placers leads to a 44% reduction in Total Overflow without compromising wirelength.

翻译：布局是现代芯片设计中关键且具有挑战性的步骤，而可布线性是衡量布局质量的重要指标。当前面向可布线性的布局器通常采用迭代式两阶段方法，其中第一阶段生成布局方案，第二阶段通过不可微的布线结果启发式地改进方案质量。这种方法阻碍了在布局过程中对可布线性进行联合优化。为解决此问题，本文提出RoutePlacer，一种端到端的可布线感知布局方法。它训练了定制的图神经网络RouteGNN，通过捕获并融合布局的几何与拓扑表示，高效准确地预测可布线性。训练后的RouteGNN可作为可布线性的可微近似，实现基于梯度的端到端可布线性优化。此外，RouteGNN可作为即插即用的替代方案，增强两阶段布局器的性能。我们在开源AI4EDA平台DREAMPlace上的实验表明，与现有最先进方法相比，RoutePlacer可在保持布线线长的同时将总溢出降低16%；将RouteGNN集成到两阶段布局器中，可在不牺牲线长的前提下将总溢出降低44%。