The escalating complexity of modern digital systems has imposed significant challenges on integrated circuit (IC) design, necessitating tools that can simplify the IC design flow. The advent of Large Language Models (LLMs) has been seen as a promising development, with the potential to automate the generation of Hardware Description Language (HDL) code, thereby streamlining digital IC design. However, the practical application of LLMs in this area faces substantial hurdles. Notably, current LLMs often generate HDL code with small but critical syntax errors and struggle to accurately convey the high-level semantics of circuit designs. These issues significantly undermine the utility of LLMs for IC design, leading to misinterpretations and inefficiencies. In response to these challenges, this paper presents targeted strategies to harness the capabilities of LLMs for digital ASIC design. We outline approaches that improve the reliability and accuracy of HDL code generation by LLMs. As a practical demonstration of these strategies, we detail the development of a simple three-phase Pulse Width Modulation (PWM) generator. This project, part of the "Efabless AI-Generated Open-Source Chip Design Challenge," successfully passed the Design Rule Check (DRC) and was fabricated, showcasing the potential of LLMs to enhance digital ASIC design. This work underscores the feasibility and benefits of integrating LLMs into the IC design process, offering a novel approach to overcoming the complexities of modern digital systems.

翻译：现代数字系统日益增长的复杂性给集成电路（IC）设计带来了巨大挑战，亟需能够简化IC设计流程的工具。大语言模型的出现被视为一项颇有前景的进展，其具有自动生成硬件描述语言代码的潜力，从而可简化数字IC设计流程。然而，LLM在此领域的实际应用仍面临重大障碍。值得注意的是，当前的LLM生成的HDL代码常存在细微但关键的语法错误，并且难以准确传达电路设计的高级语义。这些问题严重削弱了LLM在IC设计中的实用性，导致理解偏差和效率低下。针对这些挑战，本文提出了利用LLM能力进行数字ASIC设计的针对性策略。我们概述了提高LLM生成HDL代码可靠性和准确性的方法。为实际展示这些策略，我们详细描述了一个简单的三相脉冲宽度调制生成器的开发过程。该项目作为"Efabless AI生成开源芯片设计挑战赛"的一部分，成功通过了设计规则检查并完成了流片，展示了LLM在增强数字ASIC设计方面的潜力。本工作证实了将LLM集成到IC设计流程中的可行性与优势，为克服现代数字系统的复杂性提供了一种新颖方法。