Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity can affect coincidence timing and thereby influence accidental-coincidence rate and Quantum Bit Error Rate (QBER). This paper analyzes how measured FPGA-TDC nonlinearity propagates to QKD timing metrics using a conservative system-level model that combines random timing uncertainty and deterministic nonlinearity. We also propose fabric-level mitigation strategies based on LUT-assisted delay shaping and placement constraints to reduce severe bin-width irregularities without statistical calibrations. The method is evaluated by reproducing two open-source TDCs implemented on a low-cost Zynq-7000 FPGA. We observe reductions of 14\%-21\% in integral nonlinearity (INL) compared with the non-optimized design, leading to a reduced QBER contribution and an improvement by 3.7\%-14.2\% in the estimated secret fraction. These results suggest that raw FPGA-TDC nonlinearity deserves explicit consideration in timing-sensitive QKD implementations.

翻译：基于FPGA的时间数字转换器（TDC）中的固有非线性通常被视为校准问题，主要通过后校正指标进行评估。然而，在量子密钥分发（QKD）中，原始延迟线非均匀性会影响符合时序，进而影响偶然符合率和量子误码率（QBER）。本文通过结合随机时序不确定性与确定性非线性的保守系统级模型，分析了FPGA-TDC实测非线性如何传播至QKD时序指标。我们还提出了基于LUT辅助延迟整形和布局约束的制造级缓解策略，无需统计校准即可减少严重的箱宽不规则性。该方法通过复现两款在低成本Zynq-7000 FPGA上实现的开源TDC进行评估。与未优化设计相比，我们观察到积分非线性（INL）降低14%-21%，导致QBER贡献减少，预计密钥分率提升3.7%-14.2%。这些结果表明，在时序敏感的QKD实现中，原始FPGA-TDC非线性应得到明确考虑。