The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, we present a holistic pre-silicon verification and validation (V&V) methodology targeting highly robust RISC-V chip designs. This paper provides an overview of BZL's V&V approach, which integrates three complementary platforms: (1) a UVM-based verification environment to thoroughly validate RTL functionality; (2) an FPGA-based validation platform that enables system-level pre-silicon hardware-software RTL validation; and (3) a CI/CD flow that continuously automates build, deployment, and tests across these domains. By embedding these platforms into an industrial-grade V&V loop and exploiting large-scale CPU and FPGA hardware infrastructures, the BZL project enables continuous evolution of reliable hardware development and software integration. We believe that the BZL's V&V flow represents a robust and scalable foundation for ensuring the pre-silicon functional correctness and system level validation of RISC-V chip designs, and can serve as a key enabler for strategic initiatives in Europe, such as EPI and DARE, and beyond.

翻译：巴塞罗那Zetascale实验室（BZL）项目旨在强化欧洲基于RISC-V的高性能计算芯片设计与制造能力。在此背景下，我们提出了一种面向高鲁棒性RISC-V芯片设计的整体性预硅验证与确认（V&V）方法。本文概述了BZL的V&V策略，该策略整合了三大互补平台：（1）基于UVM的验证环境，用于全面验证RTL功能；（2）基于FPGA的验证平台，支持系统级预硅硬件-软件RTL验证；（3）持续集成/持续交付（CI/CD）流程，可在各领域间自动完成构建、部署和测试。通过将这些平台嵌入工业级V&V闭环，并利用大规模CPU和FPGA硬件基础设施，BZL项目实现了可靠硬件开发与软件集成的持续演进。我们认为，BZL的V&V流程为保障RISC-V芯片设计的预硅功能正确性与系统级验证提供了稳健且可扩展的基础，并可作为欧洲EPI、DARE等战略计划及其它相关领域的关键推动力。