3D field-programmable gate arrays (FPGAs) promise higher performance through vertical integration. However, existing placement tools, largely inherited from 2D frameworks, fail to capture the unique delay characteristics and optimization dynamics of 3D fabrics. We introduce a 3D FPGA placement flow that integrates partitioning-based initialization, adaptive cost scheduling, refined delay estimation, and a simulated annealing move set -- all targeted at 3D FPGA architecture. Together, these enhancements improve timing estimates and the exploration of layer assignments during placement. Compared to Verilog-To-Routing (VTR), our experiments show geometric-mean (max) critical-path delay reductions of ~3% (~7%), ~2% (~4%), ~3% (~8%), and ~6% (~18%) for four 3D architectures: 3D CB, 3D CB-O, 3D CB-I, and 3D SB, respectively. We also achieve geometric-mean (max) routed wirelength reductions of ~1% (~3%), ~2% (~8%), < 1% (~5%), and ~5% (~10%), respectively. Our work will be permissively open-sourced on GitHub.

翻译：三维现场可编程门阵列（3D FPGA）通过垂直集成有望实现更高性能。然而，现有布局工具大多继承自二维框架，未能捕捉3D fabric独特的延迟特征和优化动态。我们提出了一种3D FPGA布局布线流程，该流程集成了基于分区的初始化、自适应代价调度、精细化延迟估计以及模拟退火移动集——所有这些均针对3D FPGA架构设计。这些改进共同提升了布局期间时序估计的准确性以及层分配的探索效率。与Verilog-To-Routing（VTR）相比，我们的实验在四种3D架构（3D CB、3D CB-O、3D CB-I和3D SB）上分别实现了约~3%（~7%）、~2%（~4%）、~3%（~8%）和~6%（~18%）的几何平均（最大）关键路径延迟缩减；同时分别实现了约~1%（~3%）、~2%（~8%）、<1%（~5%）和~5%（~10%）的几何平均（最大）布线线长缩减。本工作将在GitHub上以宽松许可开源发布。