Chip placement, a critical step in the VLSI physical design flow, directly impacts performance, power, and routability. Traditional chip placement methods, relying on analytical optimization or sequential reinforcement learning (RL), face significant challenges in modern VLSI design, including the inability to consistently satisfy hard placement constraints and the requirement for computationally expensive online training for each new circuit design. Furthermore, existing sequential decision-making paradigms often suffer from compounding errors and extreme wirelength minimization that aggressively compresses modules into dense clusters, leading to severe routing congestion hotspots and failures in downstream design stages. To address these limitations, we introduce DiffPlace, a framework that reformulates chip placement as a conditional denoising diffusion process, enabling transferable policies that generalize to unseen netlists without extensive retraining. Unlike sequential paradigms, DiffPlace simultaneously optimizes all macro positions utilizing a neural backbone equipped with vector-wise message passing to capture geometric dependencies. By prioritizing a more balanced spatial distribution of macros, our framework adopts a routability-first perspective to effectively prevent routing hotspots while maintaining competitive wirelength. To effectively handle the multi-objective nature of placement, we propose a decoupled guidance mechanism: global objectives are optimized via energy-based conditioning, while local physical constraints are actively mitigated through explicit manifold gradient injection during the reverse sampling process. Extensive experiments demonstrate that DiffPlace achieves competitive placement quality while offering superior generalization efficiency compared to state-of-the-art learning-based baselines.

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