Chip placement, a critical step in the VLSI physical design flow, directly impacts performance, power, and routability. Traditional chip placement methods, relying on analytical optimization or sequential reinforcement learning (RL), face significant challenges in modern VLSI design, including the inability to consistently satisfy hard placement constraints and the requirement for computationally expensive online training for each new circuit design. Furthermore, existing sequential decision-making paradigms often suffer from compounding errors and extreme wirelength minimization that aggressively compresses modules into dense clusters, leading to severe routing congestion hotspots and failures in downstream design stages. To address these limitations, we introduce DiffPlace, a framework that reformulates chip placement as a conditional denoising diffusion process, enabling transferable policies that generalize to unseen netlists without extensive retraining. Unlike sequential paradigms, DiffPlace simultaneously optimizes all macro positions utilizing a neural backbone equipped with vector-wise message passing to capture geometric dependencies. By prioritizing a more balanced spatial distribution of macros, our framework adopts a routability-first perspective to effectively prevent routing hotspots while maintaining competitive wirelength. To effectively handle the multi-objective nature of placement, we propose a decoupled guidance mechanism: global objectives are optimized via energy-based conditioning, while local physical constraints are actively mitigated through explicit manifold gradient injection during the reverse sampling process. Extensive experiments demonstrate that DiffPlace achieves competitive placement quality while offering superior generalization efficiency compared to state-of-the-art learning-based baselines.

翻译：摘要：芯片布局作为VLSI物理设计流程中的关键步骤，直接影响性能、功耗和可布线性。传统芯片布局方法依赖于解析优化或顺序强化学习（RL），在现代VLSI设计中面临重大挑战，包括无法始终满足硬布局约束，以及需为每个新电路设计进行昂贵的在线训练。此外，现有顺序决策范式常受复合误差影响，且过度追求线长最小化会导致模块被激进压缩成密集集群，从而在下游设计阶段引发严重布线拥塞热点和设计失败。为解决上述局限性，我们提出DiffPlace——一种将芯片布局重构为条件去噪扩散过程的框架，该框架支持可迁移策略，能够在无需大量重训练的情况下泛化至未见网表。与顺序范式不同，DiffPlace利用配备向量级消息传递的神经网络骨干同步优化所有宏单元位置，从而捕获几何依赖关系。通过优先实现更均衡的宏单元空间分布，本框架采用以可布线性为首要原则的视角，有效防止布线热点产生，同时保持有竞争力的线长。为有效处理布局的多目标特性，我们提出解耦引导机制：全局目标通过基于能量的条件优化实现，局部物理约束则在反向采样过程中通过显式流形梯度注入主动缓解。大量实验表明，与最先进的基于学习的基线方法相比，DiffPlace在实现具有竞争力的布局质量的同时，展现出卓越的泛化效率。