A quantum computing simulation provides the opportunity to explore the behaviors of quantum circuits, study the properties of quantum gates, and develop quantum computing algorithms. Simulating quantum circuits requires geometric time and space complexities, impacting the size of the quantum circuit that can be simulated as well as the respective time required to simulate a particular circuit. Applying the parallelism inherent in the simulation and crafting custom architectures, larger quantum circuits can be simulated. A scalable accelerator architecture is proposed to provide a high performance, highly parallel, accelerator. Among the challenges of creating a scalable architecture is managing parallelism, efficiently routing quantum state components for gate evaluation, and measurement. An example is demonstrated on an Intel Agilex field programmable gate array (FPGA).

翻译：量子计算模拟为探索量子电路行为、研究量子门特性以及开发量子计算算法提供了机会。模拟量子电路需要几何级数的时间和空间复杂度，这影响着可模拟量子电路的规模以及模拟特定电路所需的时间。通过利用模拟中固有的并行性并设计定制架构，可以模拟更大规模的量子电路。本文提出一种可扩展的加速器架构，以提供高性能、高并行度的加速方案。构建可扩展架构面临的挑战包括并行性管理、为门运算和测量高效路由量子态分量等。我们在英特尔Agilex现场可编程门阵列（FPGA）上进行了实例验证。