Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced simulation-based debugging. However, manual SVA authoring is labor-intensive and error-prone. While Large Language Models (LLMs) show promise, their direct deployment is hindered by low functional accuracy and a severe scarcity of domain-specific data. To address these challenges, we introduce ChatSVA, an end-to-end SVA generation system built upon a multi-agent framework. At its core, the AgentBridge platform enables this multi-agent approach by systematically generating high-purity datasets, overcoming the data scarcity inherent to few-shot scenarios. Evaluated on 24 RTL designs, ChatSVA achieves 98.66% syntax and 96.12% functional pass rates, generating 139.5 SVAs per design with 82.50% function coverage. This represents a 33.3 percentage point improvement in functional correctness and an over 11x enhancement in function coverage compared to the previous state-of-the-art (SOTA). ChatSVA not only sets a new SOTA in automated SVA generation but also establishes a robust framework for solving long-chain reasoning problems in few-shot, domain-specific scenarios. An online service has been publicly released at https://www.nctieda.com/CHATDV.html.

翻译：功能验证消耗了超过50%的集成电路开发生命周期，其中SystemVerilog断言对于形式属性验证和增强的基于仿真的调试而言不可或缺。然而，手动编写SVA既费力又容易出错。尽管大语言模型展现出潜力，但其直接部署受到低功能准确率和领域特定数据严重稀缺的阻碍。为应对这些挑战，我们提出了ChatSVA——一个基于多智能体框架构建的端到端SVA生成系统。其核心AgentBridge平台通过系统化生成高纯度数据集，支持这种多智能体方法，克服了少样本场景中固有的数据稀缺问题。在24个RTL设计上的评估表明，ChatSVA实现了98.66%的语法通过率和96.12%的功能通过率，每个设计生成139.5个SVA，功能覆盖率达82.50%。与先前最先进方法相比，功能正确性提升了33.3个百分点，功能覆盖率提升了11倍以上。ChatSVA不仅设定了自动化SVA生成的新标杆，还为解决少样本、领域特定场景中的长链条推理问题建立了稳健框架。相关在线服务已在https://www.nctieda.com/CHATDV.html公开发布。