Design automation has the potential to substantially improve the efficiency of analog integrated circuit (IC) design. However, existing algorithms and tools typically focus on individual stages, such as device sizing, placement, or routing, and still require significant manual intervention to complete the full design flow. While large language models (LLMs) have recently demonstrated remarkable success in automating digital IC design workflows, these advances cannot be directly transferred to analog IC design. Key challenges include strongly coupled performance metrics, the predominance of unstructured circuit schematic images, and the fact that most prior approaches address only isolated stages of the analog design process, limiting their ability to capture end-to-end performance impact. To address these challenges, we propose AnalogMaster, an extensible, LLM-based framework that enables end-to-end automation of analog IC design through a unified pipeline spanning circuit image-to-netlist generation, parameter optimization, placement, and routing. AnalogMaster integrates a joint reasoning mechanism that leverages in-context learning and intent reasoning to achieve accurate and robust image-to-netlist conversion. A parameter search agent integrating self-enhanced prompt engineering and context truncation is developed for effective device sizing and downstream physical design. Experimental evaluations on 15 representative circuits with varying levels of complexity demonstrate strong and consistent performance across multiple models. In particular, GPT-5 achieves success rates of 92.9% and 99.9% on Pass@1 and Pass@5, respectively. These results validate the effectiveness and robustness of the proposed framework and establish a practical paradigm for applying LLMs to full-stack analog IC design automation.

翻译：设计自动化有望显著提升模拟集成电路（IC）的设计效率。然而，现有算法与工具通常仅专注于器件尺寸确定、布局或布线等单一阶段，仍需大量人工干预才能完成完整设计流程。尽管大语言模型（LLMs）近期已在数字集成电路设计流程自动化方面展现出卓越成效，但这些进展无法直接迁移至模拟集成电路设计领域。其关键挑战包括：强耦合的性能指标、非结构化的电路原理图图像的普遍存在，以及大多数现有方法仅处理模拟设计流程的孤立阶段，从而限制了其对端到端性能影响进行建模的能力。为应对这些挑战，我们提出AnalogMaster——一个可扩展的、基于LLM的框架，通过统一流水线实现模拟集成电路设计的端到端自动化，涵盖电路图像到网表生成、参数优化、布局及布线全流程。AnalogMaster集成了联合推理机制，利用上下文学习与意图推理实现准确稳健的图像到网表转换。为有效进行器件尺寸确定及后续物理设计，我们开发了参数搜索智能体，该智能体整合了自增强提示工程与上下文截断技术。在15个复杂度各异的代表性电路上的实验评估表明，该框架在多个模型上均展现出强劲且一致的性能。特别地，GPT-5在Pass@1和Pass@5上分别取得了92.9%和99.9%的成功率。这些结果验证了所提框架的有效性与鲁棒性，并为将LLM应用于全栈模拟集成电路设计自动化建立了实用范式。