ML models are increasingly being used to increase the test coverage and decrease the overall testing time. This field is still in its nascent stage and up till now there were no algorithms that could match or outperform commercial tools in terms of speed and accuracy for large circuits. We propose an ATPG algorithm HybMT in this paper that finally breaks this barrier. Like sister methods, we augment the classical PODEM algorithm that uses recursive backtracking. We design a custom 2-level predictor that predicts the input net of a logic gate whose value needs to be set to ensure that the output is a given value (0 or 1). Our predictor chooses the output from among two first-level predictors, where the most effective one is a bespoke neural network and the other is an SVM regressor. As compared to a popular, state-of-the-art commercial ATPG tool, HybMT shows an overall reduction of 56.6% in the CPU time without compromising on the fault coverage for the EPFL benchmark circuits. HybMT also shows a speedup of 126.4% over the best ML-based algorithm while obtaining an equal or better fault coverage for the EPFL benchmark circuits.

翻译：机器学习模型正越来越多地被用于提高测试覆盖率和减少总体测试时间。该领域仍处于初期阶段，至今尚无算法能在大型电路的测试速度和准确性上匹配或超越商业工具。本文提出了一种突破这一障碍的ATPG算法HybMT。与同类方法类似，我们增强了使用递归回溯的经典PODEM算法。我们设计了一个自定义的两级预测器，用于预测需要设置值的逻辑门输入线网，以确保输出为给定值（0或1）。我们的预测器从两个一级预测器中选择输出，其中效果最好的一个是定制的神经网络，另一个是SVM回归器。与流行的、最先进的商业ATPG工具相比，HybMT在EPFL基准电路上实现了整体CPU时间减少56.6%，且未影响故障覆盖率。同时，在EPFL基准电路上，HybMT相比最佳基于ML的算法实现了126.4%的加速，并获得了相同或更优的故障覆盖率。