The history of ternary adders goes back to more than six decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This paper conducts a review of TFAs so that one can be familiar with the utilized design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0V or VDD. This way, in a single-VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favorable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, we got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this paper. Simulation results by HSPICE and 32nm CNFET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count.

翻译：三值加法器的历史可追溯至六十多年前。此后，文献中涌现出大量三值全加器（ternary full adders, TFA）。本文对TFA进行综述，帮助读者熟悉其设计方法及普遍性。尽管已有众多TFA，但几乎均非最简形式。若采用部分TFA替代完整TFA，则可消除大量晶体管。根据我们的调查，以往设计中仅28.6%为部分TFA。此外，通过假设输出进位电压为0V或VDD的部分TFA，可进一步简化设计。如此，在单VDD设计中，进位产生器部分的电压分配将得以消除，从而降低功耗。据我们所知，文献中仅有三种部分TFA符合此有利条件。同时，以往多数文章的仿真设置不够真实，导致其报告的结果既无可比性也不完全有效。因此，我们开展此项调研，阐述该问题并改进部分原有设计。本文从84篇论文中精选出10种TFA（源自11篇论文），并进行简化与仿真。采用HSPICE及32nm CNFET技术的仿真结果表明，简化后的部分TFA在延迟、功耗和晶体管数量方面均优于原始版本。