The globalization of the semiconductor industry has introduced security challenges to Integrated Circuits (ICs), particularly those related to the threat of Hardware Trojans (HTs) - malicious logic that can be introduced during IC fabrication. While significant efforts are directed towards verifying the correctness and reliability of ICs, their security is often overlooked. In this paper, we propose a comprehensive approach to enhance IC security from the front-end to back-end stages of design. Initially, we outline a systematic method to transform existing verification assets into potent security checkers by repurposing verification assertions. To further improve security, we introduce an innovative technique for integrating online monitors during physical synthesis - a back-end insertion providing an additional layer of defense. Experimental results demonstrate a significant increase in security, measured by our introduced metric, Security Coverage (SC), with a marginal rise in area and power consumption, typically under 20\%. The insertion of online monitors during physical synthesis enhances security metrics by up to 33.5\%. This holistic approach offers a comprehensive and resilient defense mechanism across the entire spectrum of IC design.

翻译：半导体产业的全球化给集成电路带来了安全挑战，尤其是硬件木马（HT）的威胁——这种恶意逻辑可能在芯片制造过程中被植入。尽管大量研究致力于验证集成电路的正确性与可靠性，但其安全性往往被忽视。本文提出了一种从前端到后端设计阶段全面增强集成电路安全性的方法。首先，我们概述了一种系统化方法，通过复用验证断言将现有验证资产转化为有效的安全检测器。为进一步提升安全性，我们引入了一项创新技术，在物理综合阶段集成在线监测器——这种后端插入机制可提供额外防御层。实验结果表明，在我们提出的安全覆盖率（SC）指标衡量下，安全性显著提升，而面积与功耗的增加幅度通常低于20%。在物理综合阶段插入在线监测器可使安全指标最高提升33.5%。这种整体性方法为整个集成电路设计流程提供了全面且鲁棒的防御机制。