Electronic Design Automation (EDA) is essential for IC design and has recently benefited from AI-based techniques to improve efficiency. Logic synthesis, a key EDA stage, transforms high-level hardware descriptions into optimized netlists. Recent research has employed machine learning to predict Quality of Results (QoR) for pairs of And-Inverter Graphs (AIGs) and synthesis recipes. However, the severe scarcity of data due to a very limited number of available AIGs results in overfitting, significantly hindering performance. Additionally, the complexity and large number of nodes in AIGs make plain GNNs less effective for learning expressive graph-level representations. To tackle these challenges, we propose MTLSO - a Multi-Task Learning approach for Logic Synthesis Optimization. On one hand, it maximizes the use of limited data by training the model across different tasks. This includes introducing an auxiliary task of binary multi-label graph classification alongside the primary regression task, allowing the model to benefit from diverse supervision sources. On the other hand, we employ a hierarchical graph representation learning strategy to improve the model's capacity for learning expressive graph-level representations of large AIGs, surpassing traditional plain GNNs. Extensive experiments across multiple datasets and against state-of-the-art baselines demonstrate the superiority of our method, achieving an average performance gain of 8.22\% for delay and 5.95\% for area.

翻译：电子设计自动化（EDA）对于集成电路设计至关重要，近年来受益于基于人工智能的技术以提高效率。逻辑综合作为EDA的关键阶段，负责将高级硬件描述转换为优化的网表。近期研究已采用机器学习来预测与-反相器图（AIG）与综合方案配对的结果质量（QoR）。然而，由于可用AIG数量极为有限导致的数据严重稀缺引发了过拟合问题，显著制约了性能表现。此外，AIG中节点的复杂性与庞大数量使得普通图神经网络在学习表达性图级表示时效果欠佳。为应对这些挑战，我们提出了MTLSO——一种用于逻辑综合优化的多任务学习方法。一方面，该方法通过在不同任务间训练模型以最大化有限数据的利用率，包括在主要回归任务之外引入二元多标签图分类的辅助任务，使模型能够从多样化的监督源中获益。另一方面，我们采用分层图表示学习策略来增强模型学习大型AIG表达性图级表示的能力，其效果超越了传统的普通图神经网络。在多个数据集上针对最先进基线的广泛实验证明了我们方法的优越性，其在延迟和面积指标上分别实现了平均8.22%和5.95%的性能提升。