Modern FPGA SoCs are no longer just collections of accelerators on top of a programmable fabric. They combine programmable logic with hardened processors, NoCs, and components that dominate end-to-end performance. Evaluating individual pieces is insufficient; system performance depends on the interplay of SoC components. However, current FPGA SoC simulations provide limited support for this style of evaluation. Vendor simulations capture these interactions but are prohibitively slow for iterative design-space exploration. At the same time, generic software models overly abstract the hardware components that determine real behavior, resulting in less accurate simulations. Fast, easy-to-use simulators that accurately model real SoCs are critical for system debugging and design space exploration. We present Naviq, an open-source, cycle-level software simulator for FPGA SoCs, tuned to AMD Versal-class architectures. Naviq bridges accurate but slow vendor simulation and fast software modeling: it captures key behaviors of modern commercial FPGA SoCs while being fast enough for debugging and design-space exploration. Naviq models hardened SoC infrastructure in C++ and integrates accelerators through Verilator, allowing designers to evaluate custom hardware in a full-system environment. At the center of Naviq is an AXI4-compliant NoC model that captures transaction ordering, packetization, routing, backpressure, and memory interactions. Naviq provides CPU and memory integration, protocol checking, checkpointing, tracing, and performance-analysis tools for debugging and design-space exploration. Experimental results show Naviq closely reproduces the bandwidth and latency of Vivado's RTL NoC model while accelerating the evaluated simulations by 81x-182x. We present five case studies demonstrating Naviq's capabilities. Naviq enables practical full-system evaluation of modern FPGA SoC designs.

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