Quantum Error Correction requires decoders to process syndromes generated by the error-correction circuits. These decoders must process syndromes faster than they are being generated to prevent a backlog of undecoded syndromes that can exponentially increase the memory and time required to execute the program. This has resulted in the development of fast hardware decoders that accelerate decoding. Applications utilizing error-corrected quantum computers will require hundreds to thousands of logical qubits and provisioning a hardware decoder for every logical qubit can be very costly. In this work, we present a framework to reduce the number of hardware decoders and navigate the compute-memory trade-offs without sacrificing the performance or reliability of program execution. Through workload-centric characterizations, we propose efficient decoder scheduling policies which can reduce the number of hardware decoders required to run a program by up to 10x while consuming less than 100 MB of memory.

翻译：量子纠错要求解码器处理由纠错电路产生的校验子。这些解码器必须以快于校验子生成的速度进行处理，以防止未解码校验子的积压——这种积压会指数级增加程序执行所需的内存和时间。这推动了加速解码的快速硬件解码器的发展。利用纠错量子计算机的应用将需要数百至数千个逻辑量子比特，而为每个逻辑量子比特配置一个硬件解码器的成本可能非常高昂。在本工作中，我们提出了一个框架，旨在减少硬件解码器的数量，并在不牺牲程序执行性能或可靠性的前提下，权衡计算与内存资源。通过以工作负载为中心的特性分析，我们提出了高效的解码器调度策略，该策略可将运行程序所需的硬件解码器数量减少高达10倍，同时消耗少于100 MB的内存。