Quantum Error Correction requires decoders to process syndromes generated by the error-correction circuits. These decoders must process syndromes faster than they are being generated to prevent a backlog of undecoded syndromes. This backlog can exponentially increase the time required to execute the program, which has resulted in the development of fast hardware decoders that accelerate decoding. Applications utilizing error-corrected quantum computers will require hundreds to thousands of logical qubits and provisioning a hardware decoder for every logical qubit can be very costly. In this work, we present a framework to reduce the number of hardware decoders and navigate the compute-performace trade-offs without sacrificing the performance or reliability of program execution. Through workload-centric characterizations performed by our framework, we propose efficient decoder scheduling policies that can reduce the number of hardware decoders required to run a program by up to 10X. With the proposed framework, scalability can be achieved via decoder virtualization, and individual decoders can be built to maximize accuracy and performance.

翻译：量子纠错需要解码器处理由纠错电路产生的校验子。这些解码器必须比校验子生成的速度更快地处理它们，以防止未解码校验子的积压。这种积压会指数级增加程序执行所需的时间，从而催生了加速解码的快速硬件解码器的开发。利用纠错量子计算机的应用将需要数百至数千个逻辑量子比特，而为每个逻辑量子比特配置硬件解码器的成本可能非常高昂。在本工作中，我们提出了一个框架，旨在减少硬件解码器的数量，并在不牺牲程序执行性能或可靠性的前提下，权衡计算与性能。通过我们框架执行的以工作负载为中心的特性分析，我们提出了高效的解码器调度策略，可将运行程序所需的硬件解码器数量减少高达10倍。借助所提出的框架，可通过解码器虚拟化实现可扩展性，并且可以构建单个解码器以最大化准确性和性能。