Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural language. This process often requires human interpretation by verification engineers to convert these specifications into functional verification assertions. Existing methods for generating assertions from natural language specifications are limited to sentences extracted by engineers, discouraging its practical application. In this work, we present AssertLLM, an automatic assertion generation framework that processes complete specification files. AssertLLM breaks down the complex task into three phases, incorporating three customized Large Language Models (LLMs) for extracting structural specifications, mapping signal definitions, and generating assertions. Our evaluation of AssertLLM on a full design, encompassing 23 I/O signals, demonstrates that 89\% of the generated assertions are both syntactically and functionally accurate.

翻译：基于断言的验证（ABV）是确保设计电路符合其架构规范（通常以自然语言描述）的关键方法。该过程通常需要验证工程师进行人工解读，将这些规范转换为功能验证断言。现有从自然语言规范生成断言的方法仅限于工程师提取的句子，限制了其实际应用。本文提出AssertLLM，一种能够处理完整规范文件的自动断言生成框架。AssertLLM将这一复杂任务分解为三个阶段，整合了三个定制化大语言模型（LLM），分别用于提取结构规范、映射信号定义以及生成断言。我们在包含23个I/O信号的完整设计上对AssertLLM进行评估，结果表明89%的生成断言在语法和功能上均准确无误。