In analog circuits, process variation can cause unpredictability in circuit performance. Common-centroid (CC) type layouts have been shown to mitigate process-induced variations and are widely used to match circuit elements. Nevertheless, selecting the most suitable CC topology necessitates careful consideration of important layout constraints. Manual handling of these constraints becomes challenging, especially with large size problems. State-of-the-art CC placement methods lack an optimization framework to handle important layout constraints collectively. They also require manual efforts and consequently, the solutions can be suboptimal. To address this, we propose a unified framework based on multi-objective optimization for CC placement of analog transistors. Our method handles various constraints, including degree of dispersion, routing complexity, diffusion sharing, and layout dependent effects. The multi-objective optimization provides better handling of the objectives when compared to single-objective optimization. Moreover, compared to existing methods, our method explores more CC topologies. Post-layout simulation results show better performance compared to state-of-the-art techniques in generating CC layouts.

翻译：在模拟电路中，工艺变化会导致电路性能不可预测。共质心型布局已被证明能够缓解工艺引起的变异，并广泛用于匹配电路元件。然而，选择最合适的共质心拓扑需要仔细考虑重要的版图约束条件。人工处理这些约束具有挑战性，尤其在大规模问题中。现有的共质心布局方法缺乏能够统一处理重要版图约束的优化框架，仍需人工干预，导致解决方案可能非最优。为此，我们提出一种基于多目标优化的统一框架，用于模拟晶体管的共质心布局。我们的方法处理多种约束条件，包括分散度、布线复杂度、扩散区共享以及版图相关效应。与单目标优化相比，多目标优化能更好地处理各目标间的权衡。此外，与现有方法相比，我们的方法能够探索更多共质心拓扑结构。后版图仿真结果表明，在生成共质心布局方面，本方法相比现有技术具有更优的性能表现。