The widespread proliferation of deep learning applications has triggered the need to accelerate them directly in hardware. General Matrix Multiplication (GEMM) kernels are elemental deep-learning constructs and they inherently map onto Systolic Arrays (SAs). SAs are regular structures that are well-suited for accelerating matrix multiplications. Typical SAs use a pipelined array of Processing Elements (PEs), which communicate with local connections and pre-orchestrated data movements. In this work, we show that the physical layout of SAs should be asymmetric to minimize wirelength and improve energy efficiency. The floorplan of the SA adjusts better to the asymmetric widths of the horizontal and vertical data buses and their switching activity profiles. It is demonstrated that such physically asymmetric SAs reduce interconnect power by 9.1% when executing state-of-the-art Convolutional Neural Network (CNN) layers, as compared to SAs of the same size but with a square (i.e., symmetric) layout. The savings in interconnect power translate, in turn, to 2.1% overall power savings.

翻译：深度学习应用的广泛普及催生了在硬件层面直接加速这些应用的需求。通用矩阵乘法（General Matrix Multiplication, GEMM）核是深度学习的基本构建模块，并且自然地映射到脉动阵列（Systolic Arrays, SAs）上。SAs是一种规则结构，非常适合加速矩阵乘法。典型的SAs采用处理单元（Processing Elements, PEs）的流水线阵列，这些单元通过本地连接和预编排的数据移动进行通信。在本工作中，我们证明SAs的物理布局应是非对称的，以最小化布线长度并提高能效。SAs的布图规划能更好地适应水平和垂直数据总线的非对称宽度及其开关活动轮廓。实验表明，与相同尺寸但采用正方形（即对称）布局的SAs相比，这种物理非对称的SAs在执行最先进的卷积神经网络（Convolutional Neural Network, CNN）层时，互连功耗降低了9.1%。进而，互连功耗的节省转化为整体功耗降低2.1%。