Logic synthesis is one of the most important steps in design and implementation of digital chips with a big impact on final Quality of Results (QoR). For a most general input circuit modeled by a Directed Acyclic Graph (DAG), many logic synthesis problems such as delay or area minimization are NP-Complete, hence, no optimal solution is available. This is why many classical logic optimization functions tend to follow greedy approaches that are easily trapped in local minima that does not allow improving QoR as much as needed. We believe that Artificial Intelligence (AI) and more specifically Reinforcement Learning (RL) algorithms can help in solving this problem. This is because AI and RL can help minimizing QoR further by exiting from local minima. Our experiments on both open source and industrial benchmark circuits show that significant improvements on important metrics such as area, delay, and power can be achieved by making logic synthesis optimization functions AI-driven. For example, our RL-based rewriting algorithm could improve total cell area post-synthesis by up to 69.3% when compared to a classical rewriting algorithm with no AI awareness.

翻译：逻辑综合是数字芯片设计与实现中最重要的步骤之一，对最终质量结果（QoR）具有重大影响。对于由有向无环图（DAG）建模的最通用输入电路，许多逻辑综合问题（如延迟或面积最小化）属于NP完全问题，因此无法获得最优解。这导致许多经典逻辑优化函数倾向于采用贪婪方法，容易陷入局部最优，无法按需提升QoR。我们相信，人工智能（AI），特别是强化学习（RL）算法，能够帮助解决这一问题。这是因为AI和RL可以通过跳出局部最优来进一步优化QoR。我们在开源和工业基准电路上的实验表明，通过使逻辑综合优化函数具有AI驱动能力，可以在面积、延迟和功耗等重要指标上实现显著改进。例如，与不含AI感知的经典重写算法相比，我们基于RL的重写算法可在综合后将总面积优化最多达69.3%。