The computation and memory-intensive nature of DNNs limits their use in many mobile and embedded contexts. Application-specific integrated circuit (ASIC) hardware accelerators employ matrix multiplication units (such as the systolic arrays) and dedicated nonlinear function units to speed up DNN computations. A close examination of these ASIC accelerators reveals that the designs are often specialized and lack versatility across different networks, especially when the networks have different types of computation. In this paper, we introduce a novel systolic array architecture, which is capable of executing nonlinear functions. By encompassing both inherent linear and newly enabled nonlinear functions within the systolic arrays, the proposed architecture facilitates versatile network inferences, substantially enhancing computational power and energy efficiency. Experimental results show that employing this systolic array enables seamless execution of entire DNNs, incurring only a negligible loss in the network inference accuracy. Furthermore, assessment and evaluation with FPGAs reveal that integrating nonlinear computation capacity into a systolic array does not introduce extra notable (less than 1.5%) block memory memories (BRAMs), look-up-tables (LUTs), or digital signal processors (DSPs) but a mere 13.3% - 24.1% more flip flops (FFs). In comparison to existing methodologies, executing the networks with the proposed systolic array, which enables the flexibility of different network models, yields up to 25.73x, 5.21x, and 1.54x computational efficiency when compared to general-purpose CPUs, GPUs, and SoCs respectively, while achieving comparable (83.4% - 135.8%) performance with the conventional accelerators which are designed for specific neural network models.

翻译：深度神经网络（DNN）的计算密集型和内存密集型特性限制了其在众多移动及嵌入式场景中的应用。专用集成电路（ASIC）硬件加速器采用矩阵乘法单元（如脉动阵列）和专用非线性函数单元来加速DNN计算。对这类ASIC加速器的细致分析表明，其设计往往具有专用性，且在不同网络（尤其是包含不同类型计算任务的网络）间缺乏通用性。本文提出一种新颖的脉动阵列架构，该架构能够执行非线性函数。通过将固有的线性运算与新增的非线性功能集成于脉动阵列内，所提架构支持多种网络的推理任务，显著提升了计算能力与能效。实验结果表明，采用该脉动阵列可实现整个DNN的无缝执行，且网络推理精度损失可忽略不计。此外，基于FPGA的评估与验证显示，将非线性计算能力集成至脉动阵列，不会显著增加块内存（BRAM）、查找表（LUT）或数字信号处理器（DSP）资源（增幅小于1.5%），而仅需额外增加13.3%至24.1%的触发器（FF）。与现有方法相比，使用所提脉动阵列执行网络（可灵活适配不同网络模型），其计算效率相比通用CPU、GPU及片上系统（SoC）分别提升最高达25.73倍、5.21倍和1.54倍，同时可实现与专为特定神经网络模型设计的传统加速器相当的性能（83.4%至135.8%）。