We present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting (PRAC), described in JEDEC DDR5 specification's April 2024 update. Unlike prior state-of-the-art that advises the memory controller to periodically issue refresh management (RFM) commands, which provides the DRAM chip with time to perform refreshes, PRAC introduces a new back-off signal. PRAC's back-off signal propagates from the DRAM chip to the memory controller and forces the memory controller to 1) stop serving requests and 2) issue RFM commands. As a result, RFM commands are issued when needed as opposed to periodically, reducing RFM's overheads. We analyze PRAC in four steps. First, we define an adversarial access pattern that represents the worst-case for PRAC's security. Second, we investigate PRAC's configurations and security implications. Our analyses show that PRAC can be configured for secure operation as long as no bitflip occurs before accessing a memory location 10 times. Third, we evaluate the performance impact of PRAC and compare it against prior works using Ramulator 2.0. Our analysis shows that while PRAC incurs less than 13.4% performance overhead for today's DRAM chips, its performance overheads can reach up to 63.2% for future DRAM chips that are more vulnerable to read disturbance bitflips. Fourth, we define an availability adversarial access pattern that exacerbates PRAC's performance overhead to perform a memory performance attack, demonstrating that such an adversarial pattern can hog up to 79% of DRAM throughput and degrade system throughput by up to 65%. We discuss PRAC's implications on future systems and foreshadow future research directions. To aid future research, we open-source our implementations and scripts at https://github.com/CMU-SAFARI/ramulator2.

翻译：我们首次对JEDEC DDR5规范2024年4月更新中描述的最先进片上DRAM读取干扰缓解方法——行激活计数（PRAC）——进行了严格的安全性、性能、能耗和成本分析。与先前建议内存控制器周期性发出刷新管理（RFM）命令（为DRAM芯片提供执行刷新操作的时间）的技术不同，PRAC引入了一种新型退避信号。该退避信号从DRAM芯片传播至内存控制器，强制内存控制器：1）停止服务请求；2）发出RFM命令。因此，RFM命令仅在需要时发出而非周期性发出，从而降低了RFM的开销。我们通过四个步骤分析PRAC：首先，定义代表PRAC安全最坏情况的对抗性访问模式；其次，研究PRAC的配置方案及其安全影响。分析表明，只要在访问内存位置10次之前不发生比特翻转，PRAC即可配置为安全运行模式；第三，使用Ramulator 2.0评估PRAC的性能影响并与现有研究对比。分析显示，虽然PRAC对当前DRAM芯片造成的性能开销低于13.4%，但对于未来更易受读取干扰比特翻转影响的DRAM芯片，其性能开销可能高达63.2%；第四，定义加剧PRAC性能开销的可用性对抗访问模式以实施内存性能攻击，证明此类对抗模式可占用高达79%的DRAM吞吐量，并使系统吞吐量下降达65%。我们探讨了PRAC对未来系统的影响并展望了未来研究方向。为促进后续研究，我们在https://github.com/CMU-SAFARI/ramulator2开源了实现代码与脚本。